library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( 
R 	: in std_logic_vector (7 downto 0);
S 	: in std_logic_vector (7 downto 0);
Cin: in std_logic;
operacion: in std_logic_vector (2 downto 0);
F  : buffer std_logic_vector (7 downto 0);
boverflow : out std_logic;
bsigno : out std_logic;
bcero : out std_logic;
bacarreo :out std_logic);
--Z : buffer std_logic_vector(7 downto 0));
end ALU;

architecture Behavioral of ALU is
--shared variable Z : std_logic_vector(7 downto 0);

begin

process (operacion)
begin
	if operacion = "000"
		then F <= R+S+cin; 
	end if; 
	
	if operacion = "001"
		then F <= S-R-cin; 
	end if; 
	
	if operacion = "010"
		then F <= R-S-cin; 
	end if;

	if operacion = "011"
		then F <= R OR S; 
	end if;	
	
	if operacion = "100"
		then F <= R AND S; 
	end if;	
	
--	if operacion = "101"
--		then F <= NOT(R) AND S; 
--	end if;
	
	if operacion = "110"
		then F <= R XOR S; 
	end if;

	if operacion = "110"
		then F <= R XNOR S; 
	end if;
end process;

process (F,R,S)
begin
	
	bcero <= '0'; 
	bsigno <= '0';
	boverflow <= '0';
	bacarreo <= '0';
		if F = "00000000"
			then bcero <= '1';
		end if;

		if (R(7)='0' and S(7)='0' and F(7)='1') or (R(7)='1' and S(7)='1' and F(7)='0')
			then  boverflow <= '1';
					bsigno <= '0';
		elsif F(7) = '1' 
			then  bsigno <= '1';
		end if;

end process;


end Behavioral;